ucb-bar/chipyard

Chipyard is an open-source framework for designing and simulating RISC-V-based systems-on-chip using the Chisel hardware description language. It provides a modular infrastructure for generating, simulating, and synthesizing hardware designs across FPGA and VLSI flows, supporting diverse processor cores and accelerators. The system integrates with simulation environments like FireSim and Spike, offering comprehensive tooling for verification, power analysis, and tapeout preparation.

This period focused on establishing and expanding the Chipyard framework, introducing new generator submodules for diverse processor cores and accelerators. The team also built out comprehensive simulation, VLSI, and testing infrastructure, while updating underlying toolchains and dependencies to support agile development workflows.

16 changes

This period focused on expanding Chipyard's hardware abstraction and physical implementation capabilities. The team introduced a modular configuration system, comprehensive clocking infrastructure, and support for multiple FPGA platforms including VCU118 and Arty boards.

13 changes

This period focused on expanding hardware support by adding configurations for multiple FPGA boards (VC707, Arty100T, Nexys Video, Datastorm) and integrating the FireSim simulation framework. The work also included adding new simulation backends for Xcelium and Spike, alongside refactoring the test harness infrastructure to support multi-chip topologies and decoupled IO binding.

20 changes

ucb-bar/chipyard was measured the same way every project in this corpus was: the same rubric, at a pinned commit, with the result published in full. Point the surveyor at a repository you know and see whether you agree with it.